A Technique for Testing Network Connections in Parallel with Mesh Topology
Abstract. In this paper, we connections between switches in the mesh network topology in a parallel way we've tested. The method is based on a built-in self-test, the use of buffers FIFO Each of the switches, test all connections between switches is done in parallel, not only test application time, but the area overhead of the network is reduced.
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W. Chen, SK Gupta, MA Breuer, "Test Generation for Crosstalk-induced Delay in Integrated Circuits," in Proceeding IEEE international conference test, Oct. 1999, pp. 191-200. 4 TPG / TDEs per switch (#gates) 2404 4 comparators per switch (#gates) 620 TDG (#gates) 287 TPG by reusing buffer (#gates) 352 68 Controller (#gates) our BIST method 1121 81